Generally, this invention pertains to electronic design automation (EDA) rule checking systems. More specifically, the invention pertains to rule checking systems that traverse netlists from node to node and determine whether any rules are violated and thereby validate electronic designs.
A rule-based checking system determines whether an electronic design meets particular design criteria. The rules used in the checking system identify design problems and report them to the user (e.g., designer). Typically, the checking system can identify such problems relatively early in the EDA process, during the design phase, prior to hardware testing. Thus, the rules act on a “high-level” representation such as a netlist or HDL representation, typically before the design has been mapped to hardware. In the case of a netlist, the rules act on the information contained in the individual logic nodes of a netlist and the associated netlist characteristics such as the connectivity between nodes.
Various products are available to perform rule checking on netlists or hardware design language representations of an electronic design. The MaxPlus II EDA software from Altera Corporation (San Jose, Calif.) is one example of a successful product that incorporates a design rule checking system. LEDA from Synopsys of Mountain View, Calif. is another example of a design rule checking system.
Although rule checking systems have proven to be cost effective in identifying and reporting design problems, there are continuing efforts to increase the speed and flexibility of these systems. One persistent issue in rule checking systems is the CPU time required to execute the individual design rules. Generally, each rule is a separate self-contained software function. Thus, the rule includes all logic for moving between the various nodes of a netlist and for extracting the netlist information needed to evaluate the rule. For example, a rule for determining whether all input pins meet particular connectivity requirements, must include not only the logic for making this determination, but also logic for identifying each node to test and logic for extracting the required connectivity information from each node it visits. Unfortunately, each time a rule function encounters a new node, it consumes valuable CPU cycles extracting the information it needs from the node. As a result, common information may be extracted repetitiously over a given set of rules. Therefore, as shown on graph 700 of FIG. 7A, the compilation time increases proportionally with the number of rules executed.
Another persistent issue is the lack of flexibility to easily modify existing rules or enter custom rules. Currently, EDA software vendors often predetermine the set of rules to be used with a rule checking system. Occasionally, EDA software vendors allow the user to enter custom rules. However, the entry is via a scripting format that is difficult to use. As such, a user is often restricted to use only those base rules and has no easy ability to either customize them or enter a new set of rules based on the user's choice.
Further, existing rule checking systems do not adequately supports rules that require information from a plurality of logic nodes, particularly information contained in neighboring logic nodes. But as electronic designs become more complex, many logic nodes are systematically linked with one another and therefore contain information that is necessary for determining whether certain other nodes meet particular design criteria. Currently, in order to access this information, existing rule checking systems implement an exhaustive search and loop technique that is time consuming and is susceptible to repeated extractions of the same information in neighboring logic nodes. Hence, rule checking systems cannot efficiently execute moderately complex rules that consider connectivity spanning multiple nodes.
What is needed therefore is an improved rule checking system for EDA software that efficiently checks electronic designs and allows flexible easy entry of new rules as situations warrant.